Variable Boost Converter

For my Power Electronics class, I took on the project of designing a boost converter circuit. The specifications of the project were that the converter was to have an adjustable output voltage dependent on the state of a variable potentiometer. The maximum output voltage was to occur when the potentiometer is in its most resistive state and the minimum output voltage was to occur in its least resistive state. The circuit that I designed uses a similar signal triggering mechanism to that of my previous buck converter project, in which a 555 timer is utilized as the switching signal. Since my last post, my LTspice skills have significantly improved, and I have learned how to import certain spice models to get the correct behavior out of the circuits that I use. In this new project, I’ve imported the FQP30N06 spice model from https://www.onsemi.com/download/models/lib/fqp30n06.lib. This spice model allows for the proper modeling of the FQP30N06 Mosfet, with all of its characteristics built in. This model is extremely close to the real-world model that is observed.

Theory:

555 Timer:

To begin with understanding how this circuit works, it will be helpful first to establish how a 555 timer works, specifically when it is in astable operation. The core of how a 555 timer works is through capacitor charging and discharging relationships and comparators. Taking a look at the picture below depicting the internal components of how a 555 timer operates, we can see what causes a 555 timer to operate in its astable mode (Figure 1):

Working from the output side of the 555 IC, when the output voltage is high, Q is high, meaning Q1 is turned off, thus C begins charging to Vcc through the resistors RA and RB. Vc (capacitor voltage) will charge to VTL (which is 1/3 * Vcc), causing the comparator 2 output to go high, which will make the Flip-flop S pin high, causing the Q to go high, keeping output voltage high. No change is noticed when this happens as we assumed the circuit to start high, so effectively no change is observed. The capacitor voltage continues to charge until Vc = VTH (which is 2/3 * Vcc), which turns comparator 2 output to low and turns comparator 1 output high, making the R pin on the Flip-flop high. This causes Q to go low, turning Q1 on and making the capacitor discharge toward a voltage of roughly 0.4V through RB. When Vc discharges to equal VTL, comparator 1 output turns low, comparator 2 output turns high, setting the S pin on the flip-flop high, causing Q to go high. This in turn cuts Q1 off, which causes the capacitor to start charging back towards Vcc. This cycle will repeat indefinitely unless the components involved in this circuit are disturbed or power is cutoff for this circuit.

The output behavior (Vo) of a 555 timer can be expressed through the following four parameters: Frequency (f), which represents the number of times per second the waveform completes a period, Duty Cycle (D), which represents the ratio of the amount of time the output is high divided by one period of the waveform, Time High (TH), which represents the amount of time that the waveform is high over a period, and Time Low (TL), which represents the amount of time that the waveform is low over a period. An example of the analysis used to determine the resistors (RA & RB) needed for a 555 timer operating in astable mode, changing at a frequency of 45kHz, a duty cycle of 50%, utilizing a 100pF capacitor is shown below (Figure 2):

This analysis utilizes the equation of natural charging and decaying of a capacitor’s voltage to determine the desired characteristics of our 555 timer circuit. This analysis isn’t needed for every design iteration of a 555 timer PWM generator, as we can instead use some helpful shortcut equations for the desired parameters, shown in the below figure (Figure 3):

Plugging in our previously found values of RA, RB, and C into the above equations results in the design parameters that we wanted, duty cycle = 0.5 (50%) and frequency ≈ 45kHz.

There is however a catch to using this circuit configuration for an astable mode 555 timer. The duty cycle for this setup can never be below 50%, as if we take RA = 0Ohm, duty cycle = 0.5, if RA = ꝏ, duty cycle ≈ 1, if RB = 0, duty cycle = 1, and if RB = ꝏ, duty cycle ≈ 0.5. To achieve a duty cycle lower than 50%, another circuit configuration has to be used to achieve this behavior. The circuit layout is shown in the below figure (Figure 4):

The way that this circuit differs from the standard 555 timer circuit configuration is that two diodes are placed in the direction of the charging/discharging action of the capacitor. What this does is isolates the resistors such that during the capacitor’s charging period, only RA (R1 in Figure 4) is involved, and during the capacitor’s discharging period, only RB (R2 in Figure 4) is involved. Now, if we take a look at the updated formula for duty cycle, we see that when RA (R1) = 0Ohm, duty cycle = 0, if RA = ꝏ, duty cycle ≈ 1, if RB (R2) = 0, duty cycle = 1, and if RB = ꝏ, duty cycle ≈ 0. Thus, the higher we have our RB value compared to the value of RA, the lower our duty cycle will be.

Boost Converter:

A boost converter is a DC-DC voltage converter that takes a lower input voltage and “boosts” it up to a higher output voltage. The need for a boost converter is facilitated in power electronics as it is an efficient and simple method to create a higher output voltage from a lower input voltage. Due to their component composition and switching behavior, boost converters are extremely efficient, so it is typically assumed that Pin ≈ Pin, thus giving an approximate output current as being equal to Pin / Vout. The general circuit for a boost converter is shown in the figure below (Figure 5):

The operating behavior of a boost converter is through switching action, an inductor, and a filtering capacitor. To achieve this switching action, the circuit takes advantage of the cutoff and saturation region of a transistor (N-type MOSFET typically). When a large enough positive voltage is applied to the input pin on the transistor, current begins to flow through the inductor, storing energy in its magnetic field. During this charging phase, the inductor opposes the sudden change in current, allowing it to ramp up gradually. In the absence of an input voltage (0V) on the input pin of the transistor, the transistor turns off and in turn causes the inductor’s stored magnetic field to begin to collapse. In this state, the inductor acts as source of current for the output load, with a filtering capacitor placed in parallel to filter the DC component of the switching action. This process repeats for every period of the PWM signal.

Equations and output waveforms of a boost converter’s behavior can be seen in the figure below (Figure 6):

Design:

For this project, I wanted to design a buck converter that could supply a 200Ω load at a maximum output voltage of 12V with a ripple voltage < 1.7% (20mV), given an input voltage of 5V and a switching frequency of 60kHz. The input and output parameters for this were chosen arbitrarily, but these values are typical for a power boost converter. To achieve the design for this, design calculations had to be performed to determine the proper inductor, capacitor, and ripple values. To achieve an output voltage of 12V, an equation relating output voltage to input voltage and duty cycle was used. For an input voltage of 5V and an output of 12V, it was determined that a duty of 0.583 would achieve this voltage output. At an output voltage of 12V and a load of 200Ω, the average output current would be 60mA, and via the previously found duty cycle and a formula relating output current to input current and duty cycle, it was found that at an output of 12V, the input current would be 144mA. To deal with some of the nasty effects that can come with a small inductor ripple current while also keeping a good compromise on inductor sizing, the decision was made to design for a ripple current of 30% of the average input current (read more on that here: https://www.analog.com/en/resources/technical-articles/selecting-the-right-inductor-current-ripple.html). This yielded a ripple current of ~43mA. Based on the ripple current, input voltage, duty cycle, and switching frequency, the inductance needed to have these values was an inductor of 1.125mH. To achieve a ripple voltage of 20 mV, a calculation was performed using a formula that relates the required capacitance to the specified output current, duty cycle, frequency, and ripple voltage. This yielded a capacitor value of 29.15μF. The calculations and formulas used in these calculations can be seen below (Figure 7):

Using the above design calculations as a guideline, I constructed a circuit schematic for the boost portion of the boost converter, utilizing circuit components that I had readily available to me. The components that I comprised the circuit from consisted of a FQP30N06L (N-type MOSFET) for the transistor, two 470μH inductors, one 220μH inductor, one 1N5819 schottky diode, three 10μF ceramic capacitors, and a 200Ω load resistor. The schematic for the overall boost circuit and its resultant output waveforms for theoretical duty cycle of 0.583 and 0 are shown in the figures below (Figures 8-11):

To achieve the maximum switching speed and duty cycle found above, I knew that the 555 timer configuration would have to yield a duty cycle ranging from ~0 to 0.583 at a frequency of 60kHz. To accomplish the variability of duty cycle, a potentiometer was used to adjust the RA and RB values such that when fully rotated clockwise, the maximum duty cycle of ~0.583 is achieved and when fully rotated counterclockwise, the minimum duty cycle of ~0 would be achieved. To determine the corresponding values needed to get this duty cycle range and frequency, the equations from Figure 4 were used to calculate appropriate resistor and capacitor values. The calculations for this are shown in the figure below (Figure 12):

Given these calculations, I created a circuit for the PWM signal generation side of the buck converter utilizing a NE555 timer IC, one 100kΩ potentiometer, one 1kΩ resistor, one 47kΩ resistor, one 22kΩ resistor, one 3.3kΩ resistor, two 1N4138 diodes, one 100pF ceramic capacitor, one 30pF ceramic capacitor, and one 10pF ceramic capacitor. These values were chosen as they fit standard resistor and capacitor values for real components (and they were the values that I had access to) that came close enough to the design values when put in series (resistors) / parallel (capacitors), respectively. The schematic for the overall timing circuit and its resultant output waveforms for theoretical duty cycle of 0.583 and 0 are shown in the figures below (Figures 13-16):

Results:

To verify the performance of the circuit that I created, I captured the waveforms of the output voltage of the 555 timer segment of the circuit and the output voltage of the boost converter portion corresponding to the minimum and maximum duty cycles of the 555 timer. The input voltage for the circuit was 5V and at a duty cycle of ~1.5%, the measured output voltage was around 4.79V. This aligns with the expected behavior of a boost converter, as the lower the input duty cycle, the closer to the input voltage the output voltage becomes.

At a duty cycle of ~56.2%, the measured output voltage was around 10.1V. This differs by roughly 1.7V from the observed average voltage of the simulated LTSpice circuit, likely due to several non-ideal factors: losses from circuit components, the slower than expected switching frequency of the 555 timer output, and the lower maximum duty cycle observed from the output of the 555 timer. At the same duty cycle (~56.2%), the measured ripple current was around 54.7mV, which is almost triple the expected value. The increase in ripple voltage suggests that the observed slower switching frequency may have played a large impact in the discrepancy of the observed output voltage vs expected voltage. Additional discrepancies could be attributed to sources of loss, including losses in the physical resistance of the inductors / capacitors, as well as losses due to interconnecting wires for the breadboard. The following figures show the observed waveforms and measured values for the physical circuit (Figures 17-22):

Overall, the results demonstrated that this design of a boost converter will successfully boost an input voltage of 5V to an adjustable output in a range of ≈ 4.8V – 10.1V. In the event that a higher output voltage was desired, the potentiometer value can be increased to a larger range (i.e. 200kΩ pot instead of a 100kΩ).

References:

[1] A.S. Sedra and K. C. Smith, Microelectronic Circuits, 7th ed. New York, NY, USA: Oxford University Press, 2015.

[2] B. Yang, “Multivibrators” EE 331: Fundamentals of Electronics and Semiconductors. Western Carolina University, Fall 2024. (Lecture Notes).

[3] F. Dostal, “Selecting the Right Inductor Current Ripple,” Analog Devices, Mar. 6, 2023. [Online]. Available: https://www.analog.com/en/resources/technical-articles/selecting-the-right-inductor-current-ripple.html

[4] F. Stasi, “Working with Boost Converters,” Application Report SNVA731, Texas Instruments, June 2015. [Online]. Available: https://www.ti.com/lit/an/snva731/snva731.pdf

[5] N. Mohan, Power Electronics, A First Course: Simulations and Laboratory Implementations, 2nd ed. Hoboken, NJ, USA: John Wiley & Sons, 2023.